1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly, to a semiconductor device including double insulation layers and a method of manufacturing the same.
2. Discussion of Related Art
A photolithography manufacturing method using masks corresponding to respective insulation layers has been used to form a semiconductor device that includes double insulation layers having different patterns.
An example of a semiconductor device that includes such double insulation layers is an organic light emitting display. FIG. 1 is a cross-sectional view showing an organic light emitting display. Referring to FIG. 1, a buffer layer 505 of an image display portion 500 is formed on a substrate 400. A thin film transistor and an organic light emitting diode are formed on the buffer layer 505. Here, the organic light emitting diode is connected to the thin film transistor. A pad of a pad portion 600 is formed on the buffer layer 505.
The thin film transistor includes a semiconductor layer 510, a gate insulation layer 520, a gate electrode 525, an interlayer insulating layer 530, and source/drain electrodes 541 and 545. The semiconductor layer 510 includes source/drain regions 511 and 515. The source/drain electrodes 541 and 545 are connected to the source/drain regions 511 and 515, respectively.
An insulation layer 550 is formed on the thin film transistor. In FIG. 1, the insulation layer 550 includes a passivation layer 550a and a planarization layer 550b. The organic light emitting diode is formed on the insulation layer 550 and connected to the thin film transistor through a via hole 555, which is connected to the drain electrode 545 of the source/drain electrodes 541 and 545 of the thin film transistor.
The organic light emitting diode includes an anode electrode 560, a cathode electrode 590, and an organic layer 580. The organic layer 580 is formed between the anode electrode 560 and the cathode electrode 590. A pixel division film 570 is formed on (or over) the substrate 400 and includes an opening portion 575 for exposing a part of the anode electrode 560. The anode electrode 560 includes a reflection electrode, and the cathode electrode 590 includes a transmission electrode.
In more detail, the anode electrode 560 includes a laminate film composed of a reflection film 560a and a transparent conductive film 560b. In one embodiment, the anode electrode 560 is formed of an Ag/ITO film. A first conductive pattern 527 is formed on the gate insulation layer 520 at the pad portion 600. The interlayer insulating layer 530 is formed on the gate insulation layer 520 and includes a first opening portion 537 for exposing a part of a first conductive pattern 527. A second conductive pattern 547 is formed on the interlayer insulating layer 530 to be connected to the first conductive pattern 527 through the first opening portion 537. The insulation layer 550 includes a first opening portion 557 for exposing a part of the second conductive pattern 547. As described above, the insulation layer 550 includes the passivation layer 550a and the planarization layer 550b. 
Here, the pad portion 600 includes the first conductive pattern 527 and the second conductive pattern 547. The first conductive pattern 527 is exposed by the first opening portion 537 formed at the interlayer insulating layer 530. The second conductive pattern 547 is connected to the first conductive pattern 527 through the first opening portion 537, and is exposed by the first opening portion 557 formed at the insulation layer 550. The pad portion 600 is coated with an amorphous conductive film 601 for adhesion with a connection circuit (or connection circuit board), such as a Flexible Printed Circuit (FPC).
The first conductive pattern 527 is formed by the same material as that of the gate electrode 525 of the thin film transistor, which is formed at the image display portion 500. The first conductive pattern 527 includes metal materials, such as MoW, Al, AlNd, or Cr. The second conductive pattern 547 is formed by the same material as that of the source/drain electrodes 541 and 545. The second conductive pattern 547 includes metal materials, such as MoW or Al.
In the above described organic light emitting display, the passivation layer 550a and the planarization layer 550b are provided between the thin film transistor and the organic light emitting diode as double insulation layers.
The planarization layer 550b functions to optimize a resonant structure of the organic light emitting diode by planarizing one or more layers that the planarization layer 550b is formed on (or with).
The passivation layer 550a provides a position for forming a seal between substrates of the organic light emitting display. Further, the passivation layer 550a prevents (or protects from) a wiring opening and/or a short circuit due to a scratch at the pad portion 600 and improves the dispersion of the transistor through a heat treatment. Here, the passivation layer 550a and the planarization layer 550b are shaped with different patterns.
Accordingly, to form the planarization layer of the above described organic light emitting display, a first mask process (or masking process) is required. Also, there is a need for an additional (or second) mask process to form the passivation layer.
However, since one or more additional processes, such as an etching process and a washing process, need to be performed due to the additional mask process, the additional mask process increases the overall manufacturing cost (and time) and may also damage the organic light emitting display being manufactured.